The present disclosure relates in general to integrated circuit manufacturing, and more particularly, to a system and method for sub-nanometer calibration of metrological tools. The present disclosure is also applicable with photomask fabrication.
In integrated circuit (IC) manufacturing technology, a photoresist layer is typically applied to a semiconductor wafer surface, followed by an exposure of the photoresist through a mask. A post-exposure baking process is then performed to alter physical properties of the photoresist for subsequent processing. An after development inspection (ADI) is then performed to inspect the critical dimension (CD) of the photoresist using a metrological system to determine whether it conforms to a specification. If the photoresist is within specification, a pattern is etched or transferred and the photoresist is stripped. An after etching inspection (AEI) is then performed on the wafer.
Increasingly, there is a desire to decrease the minimum feature sizes of very-large-scale integration (VLSI). Accordingly, lithography processes must provide precise CD control of photoresist patterns to avoid fluctuations in threshold voltages and line resistances associated with variations in pattern sizes that ultimately degrade circuit performance. To measure the variations in pattern sizes, scanning electron microscope (SEM), optical critical dimension (OCD), and other measurement processes are often used to assess the critical dimensions of a fabricated workpiece.
In conventional metrological techniques, a test workpiece, such as a semiconductor wafer, with a test pitch is used for calibrating metrological tools. This is achieved by having the metrological tool measure the pitch of the test wafer, which is a known value. If the measured pitch differs from the known pitch, the metrological tool is in need of calibration. The pitch of the test wafer is generally on the order of a couple hundred nanometers, e.g., 180 nm. In this regard, if the measured pitch differs from the known pitch by more than a given tolerance, the metrological tool must be recalibrated or any measurements taken by the metrological tool will be askew.
Known test wafers are constructed, as referenced above, to have photoresist lines with a pitch in excess of 100 nanometers. As such, these conventional test wafers are ineffective for calibrations less than one nanometer. Additionally, the metrological process can be damaging to the test wafer thereby requiring that several test wafers be fabricated and maintained. While it is possible to fabricate test wafers with sub-nanometer pitches, the process can be quite costly.
Therefore, it would be desirable to have a cost-effective process and apparatus for calibrating metrology tools at sub-nanometer levels.